1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, and more particularly, it relates to a method of fabricating a semiconductor device having an alignment mark used in a lithography step.
2. Description of the Prior Art
Following improvement in integration of a recent semiconductor device, an exposure method of dividing a semiconductor substrate into some regions (shots) and transferring a mask pattern every shot is employed in a lithography step for fabricating the semiconductor device. In order to accurately superpose (align) a pattern on the semiconductor substrate and a pattern on a photomask with each other in this method, the position of an alignment mark formed on the semiconductor substrate must be correctly recognized.
In general, offset (shift), scaling (scale factor) and rotation are known as factors influencing alignment accuracy. Misalignment (misregistration) results from these factors. The term “offset” stands for such a phenomenon that the pattern on the mask is transferred in a state shifting from a reference position in directions X and Y with respect to the pattern on the substrate. The term “scaling” stands for such a phenomenon that the pattern on the mask is transferred in a state enlarged or reduced in size with respect to the pattern on the substrate. The term “rotation” stands for such a phenomenon that the pattern on the mask is transferred in a state rotated about the center of the shot with respect to the pattern on the substrate.
In general, various methods are proposed in order to correct the aforementioned misalignment, as disclosed in Japanese Patent Laying-Open No. 11-54404 (1999), for example.
FIG. 9 is a flow chart for illustrating a conventional method of correcting misalignment. The conventional method of correcting misalignment is now described with reference to FIG. 9.
At a step 1 of a first process (lithography process), the result of analysis of a misalignment factor such as offset, scaling or rotation in a lithography process for a precedent lot is regarded as data for correcting a factor for a precedently processed (pilot) wafer of the current lot. The term “lot” stands for a constant quantity of semiconductor substrates collectively processed as a unit. Semiconductor substrates forming each lot are processed in each step of fabricating semiconductor devices basically at the same time or under the same conditions.
At a step 2 of the first process, the aforementioned data is input in an exposure apparatus for exposing/developing the pilot wafer with positional reference to a first alignment mark formed thereon. Thus, a resist pattern for forming a semiconductor element pattern and a resist pattern for forming a second alignment mark are formed at the same time.
At a step 3 of the first process, the first alignment mark of the pilot wafer is measured for analyzing the factor for misalignment in the lithography process for the pilot wafer.
At a step 4 of the first process, the result of analysis of the factor for the pilot wafer is confirmed and the aforementioned data is finely controlled to reduce the quantity of misalignment in the lithography process. The finely controlled data is employed as factor correction data for the remaining wafers and the next lot.
At a step 5 of the first process, the aforementioned finely controlled data is input in the exposure apparatus, for thereafter exposing/developing the remaining wafers.
At a step 1 of a second process (etching process) succeeding the first process (lithography process), etching is performed through a resist pattern serving as a mask, thereby forming the semiconductor element pattern and the second alignment mark on the semiconductor substrate.
According to the conventional method of correcting misalignment shown in FIG. 9, the quantity of misalignment can be reduced after the lithography process by feeding back the factor data in the lithography process.
In the conventional method, however, it may be difficult to reduce the quantity of misalignment after the subsequent etching process. FIGS. 10 to 13 are diagrams showing sections and partial planes in the fabrication process for illustrating the problem of the conventional method of correcting misalignment.
The problem of the conventional method of correcting misalignment is now described with reference to FIGS. 10 to 13. In the conventional process of fabricating a semiconductor device, lower semiconductor element patterns 18 and a first alignment mark 13 are simultaneously formed on a silicon oxide film 12 deposited on a silicon substrate 11, as shown in FIG. 10. The first alignment mark 13 is a reference box (outer box) of a box-in-box alignment mark, for example.
Thereafter an Al alloy film 14 is formed by sputtering, as shown in FIG. 11. When the Al alloy film 14 is formed by sputtering, the movement of atoms emitted from a target consisting of an Al alloy by sputtering has a directional property. More specifically, there is a high possibility that atoms emitted from a target located on the center of the wafer arrive at ends of the wafer from a constant oblique direction. On the side walls of the first alignment mark 13 consisting of an opening, therefore, the Al alloy film 14 grows at different rates, to result in parts 14a and 14b having different thicknesses. Consequently, the Al alloy film 14 is asymmetrically formed.
Then, a resist pattern 15a for forming an alignment mark and resist patterns 15b for forming semiconductor element patterns are formed on prescribed regions of the Al alloy film 14 by transferring a mask pattern 100. The resist pattern 15a is a mask pattern for forming a superposition box (inner box) of the box-in-box alignment mark, for example. In the lithography process shown in FIG. 12, the position of the first alignment mark 13 is detected with diffracted light of a laser beam or the like, in order to align the resist patterns 15a and 15b and the lower semiconductor element patterns 18 with each other. In this case, a detected position 16 of the first alignment mark 13 shifts rightward from the original position of the first alignment mark 13 due to the aforementioned asymmetry of the Al alloy film 14.
In this state, the steps 1 to 5 of the first process of the method of correcting misalignment shown in FIG. 9 are generally applied for accurately aligning the resist pattern 15a with the detected position 16 of the first alignment mark 13. Consequently, sizes a2 and b2 shown in FIG. 12 are substantially equalized with each other.
Then, the resist patterns 15a and 15b formed in the lithography process shown in FIG. 12 are employed as masks for etching the Al alloy film 14, thereby forming upper semiconductor element patterns 19 and a second alignment mark 17 as shown in FIG. 13.
However, the detected position 16 of the first alignment mark 13 shifts rightward from the actual first alignment mark 13 in the lithography process shown in FIG. 12, and hence the second alignment mark 17 formed with positional reference to the detected position 16 also shifts rightward with respect to the first alignment mark 13. In other words, sizes c2 and d2 are not equalized with each other.
Therefore, the upper semiconductor element patterns 19 shift rightward with respect to the lower semiconductor element patterns 18, to result in inconvenience such as defective conduction. Consequently, the semiconductor device is disadvantageously deteriorated in characteristic and reduced in yield.